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? semiconductor components industries, llc, 2013 august, 2013 ? rev. 9 1 publication order number: mc34151/d mc34151, mc33151 high speed dual mosfet drivers the mc34151/mc33151 are dual inverting high speed drivers specifically designed for applications that require low current digital circuitry to drive large capacitive loads with high slew rates. these devices feature low input current making them cmos and lsttl logic compatible, input hysteresis for fast output switching that is independent of input transition time, and two high current totem pole outputs ideally suited for driving power mosfets. also included is an undervoltage lockout with hysteresis to prevent erratic system operation at low supply voltages. typical applications include switching power supplies, dc to dc converters, capacitor charge pump voltage doublers/inverters, and motor controllers. these devices are available in dual ? in ? line and surface mount packages. features ? two independent channels with 1.5 a totem pole output ? output rise and fall times of 15 ns with 1000 pf load ? cmos/lsttl compatible inputs with hysteresis ? undervoltage lockout with hysteresis ? low standby current ? efficient high frequency operation ? enhanced system performance with common switching regulator control ics ? pin out equivalent to ds0026 and mmh0026 ? these are pb ? free and halide ? free devices figure 1. representative block diagram + + + - v cc 6 5.7v logic input a 2 logic input b 4 gnd 3 100k drive output a 7 drive output b 5 + + + + 100k http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information pdip ? 8 p suffix case 626 marking diagrams 1 8 1 8 mc3x151p awl yywwg soic ? 8 d suffix case 751 1 8 x = 3 or 4 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free package pin connections 1 8 n.c. n.c. (top view) 2 7 drive output a logic input a 36v cc gnd 4 5 drive output b logic input b 3151v alyw 1 8 (note: microdot may be in either location) 3x151 alyw 1 8 mc3x151 mc33151v
mc34151, mc33151 http://onsemi.com 2 maximum ratings rating symbol value unit power supply voltage v cc 20 v logic inputs (note 1) v in ? 0.3 to v cc v drive outputs (note 2) totem pole sink or source current diode clamp current (drive output to v cc ) i o i o(clamp) 1.5 1.0 a power dissipation and thermal characteristics d suffix soic ? 8 package case 751 maximum power dissipation @ t a = 50 c thermal resistance, junction ? to ? air p suffix 8 ? pin package case 626 maximum power dissipation @ t a = 50 c thermal resistance, junction ? to ? air p d r ja p d r ja 0.56 180 1.0 100 w c/w w c/w operating junction temperature t j +150 c operating ambient temperature mc34151 mc33151 mc33151v t a 0 to +70 ? 40 to +85 ? 40 to +125 c storage temperature range t stg ? 65 to +150 c electrostatic discharge sensitivity (esd) (note 3) human body model (hbm) machine model (mm) charged device model (cdm) esd 2000 200 1500 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. for optimum switching speed, the maximum input voltage should be limited to 10 v or v cc , whichever is less. 2. maximum package power dissipation limits must be observed. 3. esd protection per jedec standard jesd22 ? a114 ? f for hbm per jedec standard jesd22 ? a115 ? a for mm per jedec standard jesd22 ? c101d for cdm.
mc34151, mc33151 http://onsemi.com 3 electrical characteristics (v cc = 12 v, for typical values t a = 25 c, for min/max values t a is the only operating ambient temperature range that applies [note 3], unless otherwise noted.) characteristics symbol min typ max unit logic inputs input threshold voltage ? output transition high to low state output transition low to high state v ih v il ? 0.8 1.75 1.58 2.6 ? v input current ? high state (v ih = 2.6 v) input current ? low state (v il = 0.8 v) i ih i il ? ? 200 20 500 100 a drive output output voltage ? low state (i sink = 10 ma) output voltage ? low state (i sink = 50 ma) output voltage ? low state (i sink = 400 ma) output voltage ? high state (i source = 10 ma) output voltage ? high state (i source = 50 ma) output voltage ? high state (i source = 400 ma) v ol v oh ? ? ? 10.5 10.4 9.5 0.8 1.1 1.7 11.2 11.1 10.9 1.2 1.5 2.5 ? ? ? v output pulldown resistor r pd ? 100 ? k switching characteristics (t a = 25 c) propagation delay (10% input to 10% output, c l = 1.0 nf) logic input to drive output rise logic input to drive output fall t plh(in/out) t phl(in/out) ? ? 35 36 100 100 ns drive output rise time (10% to 90%) c l = 1.0 nf drive output rise time (10% to 90%) c l = 2.5 nf t r ? ? 14 31 30 ? ns drive output fall time (90% to 10%) c l = 1.0 nf drive output fall time (90% to 10%) c l = 2.5 nf t f ? ? 16 32 30 ? ns total device power supply current standby (logic inputs grounded) operating (c l = 1.0 nf drive outputs 1 and 2, f = 100 khz) i cc ? ? 6.0 10.5 10 15 ma operating voltage v cc 6.5 ? 18 v 1. for optimum switching speed, the maximum input voltage should be limited to 10 v or v cc , whichever is less. 2. maximum package power dissipation limits must be observed. 3. t low =0 c for mc34151 t high = +70 c for mc34151 ? 40 c for mc33151 +85 c for mc33151
mc34151, mc33151 http://onsemi.com 4 figure 2. switching characteristics test circuit figure 3. switching waveform definitions figure 4. logic input current versus input voltage figure 5. logic input threshold voltage versus temperature figure 6. drive output low ? to ? high propagation delay versus logic overdrive voltage figure 7. drive output high ? to ? low propagation delay versus logic input overdrive voltage v in , input voltage (v) , input current (ma) in i v cc = 12 v t a = 25 c t a , ambient temperature ( c) v th , input threshold voltage (v) v cc = 12 v upper threshold low state output lower threshold high state output v in , input overdrive voltage below lower threshold (v) t plh(in/out) , drive output propagation delay (ns) overdrive voltage is with respect to the logic input lower threshold v th(lower) v cc = 12 v c l = 1.0 nf t a = 25 c v in , input overdrive voltage above upper threshold (v) t phl(in/out) , drive output propagation delay (ns) v cc = 12 v c l = 1.0 nf t a = 25 c v th(upper) overdrive voltage is with respect to the logic input lower threshold + + + - 6 5.7v logic input 2 4 3 100k drive output 7 5 + + + + 100k 12 v 4.7 0.1 50 c l + 5.0 v 0 v 10% 90% t phl t plh 90% 10% t f t r logic input t r , t f 10 ns drive output 2.4 2.0 1.6 1.2 0.8 0.4 0 2.2 2.0 1.8 1.6 1.4 1.2 1.0 200 160 120 80 40 0 200 160 120 80 40 0 0 2.0 4.0 6.0 8.0 10 12 -55 -25 0 25 50 75 100 125 -1.6 -1.2 -0.8 -0.4 0 0 1.0 2.0 3.0 4.0
mc34151, mc33151 http://onsemi.com 5 v cc = 12 v v in = 5 v to 0 v c l = 1.0 nf t a = 25 c figure 8. propagation delay figure 9. drive output clamp voltage versus clamp current figure 10. drive output saturation voltage versus load current figure 11. drive output saturation voltage versus temperature figure 12. drive output rise time figure 13. drive output fall time 90% 10% 50 ns/div 90% 10% 10 ns/div 90% 10% 10 ns/div i o , output load current (a) v clamp , output clamp voltage (v) high state clamp (drive output driven above v cc ) v cc gnd low state clamp (drive output driven below ground) v cc = 12 v 80 s pulsed load 120 hz rate t a = 25 c i o , output load current (a) v sat , output saturation voltage(v) source saturation (load to ground) v cc = 12 v 80 s pulsed load 120 hz rate t a = 25 c v cc sink saturation (load to v cc ) gnd t a , ambient temperature ( c) v sat , output saturation voltage(v) source saturation (load to ground) sink saturation (load to v cc ) v cc = 12 v i source = 400 ma i sink = 400 ma v cc i source = 10 ma i sink = 10 ma gnd drive output logic input v cc = 12 v v in = 5 v to 0 v c l = 1.0 nf t a = 25 c v cc = 12 v v in = 5 v to 0 v c l = 1.0 nf t a = 25 c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -55 -25 0 25 50 75 100 125 3.0 2.0 1.0 0 0 -1.0 0 -1.0 -2.0 -3.0 3.0 2.0 1.0 0 0 -0.5 -0.7 -0.9 -1.1 1.9 1.7 1.5 1.0 0.8 0.6 0
mc34151, mc33151 http://onsemi.com 6 figure 14. drive output rise and fall time versus load capacitance figure 15. supply current versus drive output load capacitance figure 16. supply current versus input frequency figure 17. supply current versus supply voltage c l , output load capacitance (nf) -t , output rise\fall time(ns) t f t r t r v cc = 12 v v in = 0 v to 5.0 v t a = 25 c c l , output load capacitance (nf) i cc , supply current (ma) v cc = 12 v both logic inputs driven 0 v to 5.0 v 50% duty cycle both drive outputs loaded t a = 25 c f = 500 khz f = 200 khz f = 50 khz i cc , supply current (ma) 1 2 3 4 both logic inputs driven 0 v to 5.0 v, 50% duty cycle both drive outputs loaded t a = 25 c 1 - v cc = 18 v, c l = 2.5 nf 2 - v cc = 12 v, c l = 2.5 nf 3 - v cc = 18 v, c l = 1.0 nf 4 - v cc = 12 v, c l = 1.0 nf f, input frequency (hz) i cc , supply current (ma) v cc , supply voltage (v) t a = 25 c logic inputs at v cc low state drive outputs logic inputs grounded high state drive outputs f 80 60 40 20 0 80 60 40 20 0 80 60 40 20 0 8.0 6.0 4.0 2.0 0 0.1 1.0 10 0.1 1.0 10 100 1.0 m 0 4.0 8.0 12 16 10 k applications information description the mc34151 is a dual inverting high speed driver specifically designed to interface low current digital circuitry with power mosfets. this device is constructed with schottky clamped bipolar analog technology which offers a high degree of performance and ruggedness in hostile industrial environments. input stage the logic inputs have 170 mv of hysteresis with the input threshold centered at 1.67 v. the input thresholds are insensitive to v cc making this device directly compatible with cmos and lsttl logic families over its entire operating voltage range. input hysteresis provides fast output switching that is independent of the input signal transition time, preventing output oscillations as the input thresholds are crossed. the inputs are designed to accept a signal amplitude ranging from ground to v cc . this allows the output of one channel to directly drive the input of a second channel for master ? slave operation. each input has a 30 k pulldown resistor so that an unconnected open input will cause the associated drive output to be in a known high state. output stage each totem pole drive output is capable of sourcing and sinking up to 1.5 a with a typical ?on? resistance of 2.4 at 1.0 a. the low ?on? resistance allows high output currents to be attained at a lower v cc than with comparative cmos drivers. each output has a 100 k pulldown resistor to keep the mosfet gate low when v cc is less than 1.4 v. no over current or thermal protection has been designed into the device, so output shorting to v cc or ground must be avoided. parasitic inductance in series with the load will cause the driver outputs to ring above v cc during the turn ? on transition, and below ground during the turn ? off transition. with cmos drivers, this mode of operation can cause a destructive output latchup condition. the mc34151 is immune to output latchup. the drive outputs contain an internal diode to v cc for clamping positive voltage transients. when operating with v cc at 18 v, proper power supply bypassing must be observed to prevent the output ringing from exceeding the maximum 20 v device rating. negative output transients are clamped by the internal npn pullup transistor . since full supply voltage is applied across
mc34151, mc33151 http://onsemi.com 7 the npn pullup during the negative output transient, power dissipation at high frequencies can become excessive. figures 20, 21, and 22 show a method of using external schottky diode clamps to reduce driver power dissipation. undervoltage lockout an undervoltage lockout with hysteresis prevents erratic system operation at low supply voltages. the uvlo forces the drive outputs into a low state as v cc rises from 1.4 v to the 5.8 v upper threshold. the lower uvlo threshold is 5.3 v, yielding about 500 mv of hysteresis. power dissipation circuit performance and long term reliability are enhanced with reduced die temperature. die temperature increase is directly related to the power that the integrated circuit must dissipate and the total thermal resistance from the junction to ambient. the formula for calculating the junction temperature with the package in free air is: t j =t a + p d (r ja ) where: t j = junction temperature t a = ambient temperature p d = power dissipation r ja = thermal resistance junction to ambient there are three basic components that make up total power to be dissipated when driving a capacitive load with respect to ground. they are: p d = p q + p c + p t where: p q = quiescent power dissipation p c = capacitive load power dissipation p t = transition power dissipation the quiescent power supply current depends on the supply voltage and duty cycle as shown in figure 17. the device?s quiescent power dissipation is: p q = v cc i ccl (1 ? d) + i cch (d) where: i ccl = supply current with low state drive outputs i cch = supply current with high state drive outputs d = output duty cycle the capacitive load power dissipation is directly related to the load capacitance value, frequency, and drive output voltage swing. the capacitive load power dissipation per driver is: p c =v cc (v oh ? v ol ) c l f where: v oh = high state drive output voltage v ol = low state drive output voltage c l = load capacitance f = frequency when driving a mosfet, the calculation of capacitive load power p c is somewhat complicated by the changing gate to source capacitance c gs as the device switches. to aid in this calculation, power mosfet manufacturers provide gate charge information on their data sheets. figure 18 shows a curve of gate voltage versus gate charge for the on semiconductor mtm15n50. note that there are three distinct slopes to the curve representing different input capacitance values. to completely switch the mosfet ?on?, the gate must be brought to 10 v with respect to the source. the graph shows that a gate charge q g of 110 nc is required when operating the mosfet with a drain to source voltage v ds of 400 v. v gs , gate-to-source voltage (v) q g , gate charge (nc) c gs = q g 16 12 8.0 4.0 0 0 40 80 120 160 v ds = 100 v v ds = 400 v 8.9 nf 2.0 nf mtm15n50 i d = 15 a t a = 25 c figure 18. gate ? to ? source voltage versus gate charge v gs the capacitive load power dissipation is directly related to the required gate charge, and operating frequency. the capacitive load power dissipation per driver is: p c(mosfet) = v c q g f the flat region from 10 nc to 55 nc is caused by the drain ? to ? gate miller capacitance, occurring while the mosfet is in the linear region dissipating substantial amounts of power. the high output current capability of the mc34151 is able to quickly deliver the required gate charge for fast power efficient mosfet switching. by operating the mc34151 at a higher v cc , additional charge can be provided to bring the gate above 10 v. this will reduce the ?on? resistance of the mosfet at the expense of higher driver dissipation at a given operating frequency. the transition power dissipation is due to extremely short simultaneous conduction of internal circuit nodes when the drive outputs change state. the transition power dissipation per driver is approximately: p t = v cc (1.08 v cc c l f ? 8 y 10 ? 4 ) p t must be greater than zero. switching time characterization of the mc34151 is performed with fixed capacitive loads. figure 14 shows that for small capacitance loads, the switching speed is limited by transistor turn ? on/off time and the slew rate of the internal nodes. for large capacitance loads, the switching speed is limited by the maximum output current capability of the integrated circuit.
mc34151, mc33151 http://onsemi.com 8 layout considerations high frequency printed circuit layout techniques are imperative to prevent excessive output ringing and overshoot. do not attempt to construct the driver circuit on wire ? wrap or plug ? in prototype boards. when driving large capacitive loads, the prin ted circuit board must contain a low inductance ground plane to minimize the voltage spikes induced by the high ground ripple currents. all high current loops should be kept as short as possible using heavy copper runs to provide a low impedance high frequency path. for optimum drive performance, it is recommended that the initial circuit design contains dual power supply bypass capacitors connected with short leads as close to the v cc pin and ground as the layout will permit. suggested capacitors are a low inductance 0.1 f ceramic in parallel with a 4.7 f tantalum. additional bypass capacitors may be required depending upon drive output loading and circuit layout. proper printed circuit board layout is extremely critical and cannot be over emphasized. the mc34151 greatly enhances the drive capabilities of common switching regulators and cmos/ttl logic devices. figure 19. enhanced system performance with common switching regulators figure 20. mosfet parasitic oscillations figure 21. direct transformer drive figure 22. isolated mosfet drive series gate resistor r g may be needed to damp high frequency parasitic oscillations caused by the mosfet input capacitance and any series wiring inductance in the gate-source circuit. r g will decrease the mosfet switching speed. schottky diode d 1 can reduce the driver's power dissipation due to excessive ringing, by preventing the output pin from being driven below ground. output schottky diodes are recommended when driving inductive loads at high frequencies. the diodes reduce the driver's power dissipation by preventing the output pins from being driven above v cc and below ground. + - v cc 47 0.1 6 5.7v tl494 or tl594 2 4 3 100k 100k 7 5 v in + + ++ + + 100k 1n5819 d 1 r g v in + + 100k 100k 3 7 5 4 x 1n5819 + + + + 3 100k 1n 5819 isolation boundary
mc34151, mc33151 http://onsemi.com 9 output load regulation i o (ma) +v o (v) ? v o (v) 0 27.7 ? 13.3 1.0 27.4 ? 12.9 10 26.4 ? 11.9 20 25.5 ? 11.2 30 24.6 ? 10.5 50 22.6 ? 9.4 figure 23. controlled mosfet drive figure 24. bipolar transistor drive figure 25. dual charge pump converter the totem-pole outputs can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor c 1 . the capacitor's equivalent series resistance limits the drive output current to 1.5 a. an additional series resistor may be required when using tantalum or other low esr capacitors. in noise sensitive applications, both conducted and radiated emi can be reduced significantly by controlling the mosfet's turn-on and turn-off times. + 100k v in r g(on) r g(off) + i b + 0 - base charge removal 100k c 1 v in + - v cc = 15 v 4.7 0.1 6 5.7v 6.8 10 7 1n5819 2 + v o 2.0 v cc 47 100k 100k 5 6.8 10 1n5819 4 - v o - v cc 330pf 47 3 10k + + + + + + + + + + +
mc34151, mc33151 http://onsemi.com 10 ordering information device package shipping ? mc34151dg soic ? 8 (pb ? free) 98 units / rail mc34151dr2g soic ? 8 (pb ? free) 2500 tape & reel mc34151pg pdip ? 8 (pb ? free) 50 units / rail MC33151DG soic ? 8 (pb ? free) 98 units / rail mc33151dr2g soic ? 8 (pb ? free) 2500 tape & reel mc33151pg pdip ? 8 (pb ? free) 50 units / rail mc33151vdr2g soic ? 8 (pb ? free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc34151, mc33151 http://onsemi.com 11 package dimensions pdip ? 8 p suffix case 626 ? 05 issue n 14 5 8 b2 note 8 d b l a1 a eb e a top view c seating plane 0.010 ca side view end view end view with leads constrained dim min max inches a ???? 0.210 a1 0.015 ???? b 0.014 0.022 c 0.008 0.014 d 0.355 0.400 d1 0.005 ???? e 0.100 bsc e 0.300 0.325 m ???? 10 ??? 5.33 0.38 ??? 0.35 0.56 0.20 0.36 9.02 10.16 0.13 ??? 2.54 bsc 7.62 8.26 ??? 10 min max millimeters notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimensions a, a1 and l are measured with the pack- age seated in jedec seating plane gauge gs ? 3. 4. dimensions d, d1 and e1 do not include mold flash or protrusions. mold flash or protrusions are not to exceed 0.10 inch. 5. dimension e is measured at a point 0.015 below datum plane h with the leads constrained perpendicular to datum c. 6. dimension e3 is measured at the lead tips with the leads unconstrained. 7. datum plane h is coincident with the bottom of the leads, where the leads exit the body. 8. package contour is optional (rounded or square corners). e1 0.240 0.280 6.10 7.11 b2 eb ???? 0.430 ??? 10.92 0.060 typ 1.52 typ e1 m 8x c d1 b a2 0.115 0.195 2.92 4.95 l 0.115 0.150 2.92 3.81 h note 5 e e/2 a2 note 3 m b m note 6 m
mc34151, mc33151 http://onsemi.com 12 package dimensions soic ? 8 d suffix case 751 ? 07 issue ak 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. mc34151/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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